Concertal Announces Release of System Design Automation Capabilities NEWS
Posted on 31 October 2017
Concertal Systems, Inc., Allen, Texas, announced initial release of its new System Design Automation (SDA) technology. The company provided an early glimpse of their patent pending SDA capabilities at DAC-54, demonstrating the unique ability for system developers to quickly move from concept to commencing full chip synthesizable RTL simulation using only a common web browser, without writing any code or requiring any chip design expertise. The announced SDA release marks the successful completion of their start-up R&D effort, and provides the company’s first stable product offering to early adoption partner companies.
“Leveraging from high levels of IP reuse, Concertal SDA provides the first holistic approach to front-end FPGA and SoC (System on Chip) design” states Bob Ledzius, Concertal CEO. “We completed over 50 simple chip builds demonstrations at DAC, where we received important feedback from a full spectrum of prospective users. Our initial SDA release includes valuable new features that address expressed user needs.” Several new feature examples include:
- clock, reset, and standby IP support for low power management
- high-level behavioral C/C++ IP modeling support
- C/C++ IP bench command modeling inheritance
- improved product delivery security features and product delivery options
The company has also worked to understand and provide guidance to customers that require dove-tailing new designs into in-house UVM flows and partitioned public/private network infrastructures.
Concertal’s SDA technology engages with new design work at the earliest conceptual stage of design, automating IP functional integration and high-level verification, and further benefits IP management, back-end design flow activities, and end-silicon customer relationships.
For more information, visit www.concertal.com or contact Bob Ledzius, Founder and CEO Bob.Ledzius@Concertal.com.